Field of the Invention
The present invention relates to a semiconductor device.
Description of the Related Art
In recent years, semiconductor memory devices in which memory cells are three-dimensionally arranged to increase the degree of integration of memories have been proposed (e.g., refer to Japanese Unexamined Patent Application Publication Nos. 2007-266143 and 2013-4690).
Japanese Unexamined Patent Application Publication No. 2007-266143 discloses that a plurality of memory cells are connected in series in a vertical direction, a drain selection gate is formed above the memory cells, and a source selection gate is formed below the memory cells.
Japanese Unexamined Patent Application Publication No. 2013-4690 discloses that a plurality of memory cells are connected in series in a vertical direction, and a drain selection gate or a source selection gate is formed above the memory cells.
Therefore, according to Japanese Unexamined Patent Application Publication Nos. 2007-266143 and 2013-4690, at least one or two tiers of selection gates are formed in addition to control gates whose number of tiers is equal to that of the memory cells.
When the number of gates is increased, the number of production steps increases.
Furthermore, at least one or two selection gates are formed for each pillar-shaped semiconductor layer. The selection gate itself does not store any information. Moreover, at least one or two circuits for driving a selection gate are required for each pillar-shaped semiconductor layer.
As the width of a silicon pillar decreases, it becomes more difficult to make an impurity be present in the silicon pillar because the density of silicon is 5×1022/cm3.
In known SGTs, it has been proposed that the channel concentration is set to be a low impurity concentration of 1017 cm−3 or less and the threshold voltage is determined by changing the work function of a gate material (e.g., refer to Japanese Unexamined Patent Application Publication No. 2004-356314).
It has been disclosed that, in planar MOS transistors, the sidewall of an LDD region is formed of a polycrystalline silicon having the same conductivity type as a low-concentration layer, surface carriers of the LDD region are induced by the difference in work function, and thus the impedance of the LDD region can be reduced compared with LDD MOS transistors with an oxide film sidewall (e.g., refer to Japanese Unexamined Patent Application Publication No. 11-297984). It has also been disclosed that the polycrystalline silicon sidewall is electrically insulated from a gate electrode. The drawings show that the polycrystalline silicon sidewall is insulated from a source and a drain by an interlayer insulating film.